AI computing has gradually entered the era of ultra-large-scale GPU clusters, where massive data interaction within super-nodes has become the norm. The limitations of traditional electrical interconnects in terms of transmission distance and signal integrity have become increasingly apparent, while pluggable optical modules used for inter-node interconnects also face bandwidth density and power consumption bottlenecks. Exploring new optical interconnect technologies has become an inevitable path for the continuous expansion of computing clusters.
Accelink's new-generation 6.4T NPO optical engine will debut at CIOE 2026, targeting next-generation AI scenarios to deliver high-speed, high-density optical interconnect solutions.
Current mainstream optical interconnect solutions are dominated by pluggable modules, where there is a long electrical channel between the ASIC/SerDes and the optical module. As per-channel rate and port density continue to increase, the pressure on pluggable solutions in terms of signal integrity and power consumption continues to intensify. CPO, by co-packaging the optical engine with the switch chip, significantly shortens the electrical interconnect distance and effectively improves interconnect density, but also imposes higher requirements on packaging integration, thermal design, reliability, and serviceability. The NPO architecture, on the basis of achieving short electrical links, low power consumption, and high-density interconnects, also delivers excellent system-level maintainability; meanwhile, it can leverage mature optical module industry chain resources to ensure supply diversity and stability, making it a more balanced and preferred path in the evolution of AI cluster optical interconnects.
Born for High-Density AI Interconnects: Four Key Features of the 6.4T NPO
The 6.4T NPO optical engine on display adopts a transceiver-integrated silicon photonic chip, linear direct-drive EIC, and pluggable Socket interface on the design end. Combined with 2.5D Flip-Chip packaging technology and multi-channel high-precision coupling technology, through full-link system design, it systematically solves three core engineering challenges: high-density multi-channel signal integrity, high-power-density thermal management, and multi-channel high-precision optical alignment.
Optical Side | Transceiver-Integrated Silicon Photonic PIC：High-density optoelectronic integration, supporting 32x200G parallel channels.
Electrical Side | Linear Direct-Drive EIC：Co-designed for near-package links, the linear architecture effectively reduces power consumption per bit.
Packaging | 2.5D Flip-Chip：Adopts 2.5D advanced packaging to achieve high-speed electrical interconnection between chips, while simultaneously completing multi-channel fiber array optical coupling integration.
Interface | Pluggable Socket：Balances ecosystem flexibility, production yield, and system maintainability.
From 3.2T to 6.4T: Full-Stack Capability Continuously Evolving
The NPO interconnect solution is not a single optical engine device, but a system-level engineering project covering external light sources, fiber management, connectors, thermal design, and full-link testing and verification. Following the industry's first full-system verification of the 3.2T silicon photonic single-mode NPO in March 2026, Accelink now releases the brand-new 6.4T NPO product. The solution adopts a 32x200G architecture, with the OE optical engine at its core, coordinated with the ELSFP external light source and FMU-Shuffle fiber management unit, to create an end-to-end NPO optical interconnect full-stack solution, achieving bandwidth density upgrades while ensuring system maturity and engineering feasibility.
